1. Field of the Invention
The present invention relates to the utilization of ceramic layers as patterning layers. More particularly, it relates to the use of ceramic layers to produce metal interconnect structures that are part of integrated circuits and microelectronic devices. Two primary advantages are provided by this invention. First, the processing of the ceramic layers is facile as films can be applied by any solvent based process, e.g., spin coating. Second, the unique chemical compositions of the ceramic layers provides substantial chemical contrast between typical layers that are applied by solution based processes.
2. Background Art
The utilization of hardmask patterning layers and buried etch stops is commonly used for the fabrication of metal interconnect structures, that are part of integrated circuits and microelectronic devices. A number of attributes are often required for the successful utilization of these layers. First, they should be definable by dry etching processes (e.g., reactive ion etch) with the use of lithographic masks and have compositions that provide chemical contrast to other layers so that structures can be easily generated. Second, they may be required to be resistant to photoresist rework steps, such as oxidizing plasmas, reducing plasmas, acidic wet baths, etc., that may be needed in cases where misalignment of patterning layers occur. Third, they must exhibit thermal stability so that they can withstand other processes that require elevated temperature processing. Fourth, they need sufficient adhesion to adjacent layers in order to withstand planarizing steps and other processes that produce stress on the interconnect structure. Depending on their placement and use, they may be required to either be removable with reasonable chemical mechanical polishing (CMP) rates or serve as a stop layer for chemical mechanical polishing. If these layers, are contained in the final interconnect structure, the dielectric constants must be low in order to minimize resistance-capacitance (RC) delays and enhance performance. Finally, they should be processable in a quick and cost effective manner.
Typically, hardmask patterning layers and buried etchstops are dielectrics systems that are deposited by chemical vapor deposition (CVD) and related methods. Although these processes allow the deposition of films having a variety of compositions including silicon oxides, silicon carbides, silicon nitrides, silicon carbonitrides, etc., they often involve costly manufacturing tools and can be process intensive and time consuming. In some cases, application of spin-on dielectrics have been proposed. However, these cases have been primarily limited to silsequioxanes, siloxanes, and other related chemistries that are primarily based on silicon-oxygen bonds.
This invention relates to ceramic structures and processing methods that are utilized in the manufacture of interconnect structures employed in any microelectronic device including: high speed microprocessors, application specific integrated circuits (ASICs), and memory storage. The utilization of ceramic patterning layers, which provide ease in processing, thermal stability, reworkability, and chemical contrast between other patterning layers, are advantageous as they reduce manufacturing costs and allow the generation of interconnect structures in a reliable manner.
In the first embodiment of this invention, structures having patterned ceramic layers on a substrate are described. The substrate in the first embodiment includes at least one layer that is intended for patterning. This layer is comprised of either metal or dielectric and may be either a uniform film or a patterned film. Underlying this layer, the substrate comprises of at least one conducting metal feature, formed on the substrate, with the substrate further comprising at least one insulating layer surrounding the conducting metal feature. The insulating layer may surround the at least one conducting metal feature at its bottom, top, and lateral surfaces. The substrate may further comprise at least one conductive barrier layer formed on at least one interface between the insulating layer and the at least one conducting metal feature. The combination of the at least one conducting metal feature and the insulating layers, may be repeated to form a multilevel interconnect stack.
The structure may be one of a silicon wafer containing microelectronic devices, a ceramic chip carrier, an organic chip carrier, a glass substrate, gallium arsenide, silicon carbide, gallium, or other semiconductor wafer.
In the first example of the first embodiment of this invention, structures having a single patterned ceramic layer are described. The single patterned ceramic layer may act as a single hard mask. In the second example of the first embodiment of this invention, structures having a clustered patterned ceramic layer are described. The clustered hard mask may comprise of at least two silicon containing dielectrics having two distinct patterns. In each of these embodiments, the ceramic layer(s) are placed on a substrate where they can be utilized to define at least one feature in the underlying structures by an etch processes step.
In the third example of the first embodiment of this invention, structures having a patterned buried etch stop are described. The buried etch stop contributes to defining the line and via levels of an interconnect structure and facilitates the generation of interconnect structures. This structure is comprised of a patterned film stack comprised of at least one dielectric layer on top of a buried etch stop, where the pattern is identical to each of these layers, and where the patterned film stack is placed on top of a substrate.
In the second embodiment of this invention, a method to generate hardmask patterning layers and buried etch stops is described. A polymeric preceramic precursor is dissolved in a suitable solvent and coated onto a substrate, having at least one film layer that is intended for patterning, to produce a film. The polymeric preceramic precursor film is converted into a ceramic patternable layer by any suitable process including thermal annealing, electron beam irradiation, ion irradiation, irradiation with ultraviolet and/or visible light, etc. During this process, the polymeric preceramic precursor may crosslink into a rigid, insoluble matrix.
Applied as a hardmask patterning layer, the ceramic patternable layer may be patterned by lithographic techniques (known in the art) and etched by dry etch processes (known in the art) to transfer the lithographic pattern into the ceramic patternable layer to generate a patterned ceramic film. Subsequent, processing steps may include a repetition of these steps along with other commonly used processes known in the art to generate interconnect structures for microelectronic devices. The ceramic patterning layer may be utilized as a clustered hardmask.
Applied as a buried etch stop, the ceramic patternable layer is generated in the same manner as described above. At least one dielectric layer is then applied onto the ceramic patternable layer, where the ceramic patternable layer is a buried etch stop. These dielectric layers are then patterned using conventional lithographic and etch process steps. The buried etch stop, which is chemically different from the dielectric layers placed on top of it serves as a stop layer, where the etch of the dielectric layers can be performed in a controllable fashion and dictates the depth of etch in the structure.
The polymeric preceramic precursor is a polymer molecule that is soluble in an organic solvent, can be applied as a coating by a solvent based process, and contains silicon. The polymeric preceramic precursor can also be a mixture of two or more polymeric components and can have any chain architecture. The polymeric preceramic precursor may be comprised of a polymer where the backbone is primarily comprised of Sixe2x80x94N and/or Sixe2x80x94C bonds. The polymeric preceramic precursor may be selected from systems having silicon including: polysilazanes, polycarbosilanes, polysilasilazane, polysilanes, polysilacarbosilanes, polysiloxazanes, polycarbosilazanes, polysilylcarbodiimides, and polysilacarbosilazanes. The polymeric preceramic precursor may be comprised of a polymer where the backbone is primarily comprised of Cxe2x80x94C bonds; an example of which is polysilylcarbodiimides.
The polymeric preceramic precursor is applied by any solvent based process to form a coating. The solvent based process involves the use of a solution of the polymeric preceramic precursor to generate this coating, where various organic solvents suitable for coating can be used. In addition, additives such as adhesion promoters and antistriation agents can be added to this solution to improve adhesion and coating quality, respectively.
The ceramic patterning layer, that is converted from the film comprised of the polymeric preceramic precursor, comprises of a silicon based material and is thermally stable to temperatures of about 300xc2x0 C. ( less than 1% weight loss/hr). The ceramic patterning layer may be crosslinked and insoluble to organic solvents. Preferably, the ceramic patterning layer may be resistant to processes used to rework (i.e., remove) patterned photoresist layers, including dry etches based on plasmas generated from O2, N2, Ar, He, Ne, H2, or combinations thereof, and wet etches such as acidic and basic solutions.
The ceramic patterning layer, may have a dielectric constant that is less than about 3.3, preferably less than about 2.8, and most preferably about 2.6. The ceramic patterning layer, may also contain porosity that further reduces the dielectric constant. When porosity is introduced to the ceramic patterning layer the dielectric constant can be reduced to less than about 2.6, most preferably to about 1.6. The pores may be generated by the removal of a sacrificial moiety that may be polymeric. The pores may also be generated by a process that involves the elimination of a high boiling point solvent. The pores may have a size scale of about 0.5 nm to about 20 nm and may have a closed cell morphology.
The ceramic patterning layer is processed to produce a patterned ceramic layer by any process known in the art including those that involving optical lithography, imprint lithography, and reactive ion etch. The multilayer substrate in which the ceramic patterning layer is utilized as either a hardmask layer or buried etchstop layer may further include any material layer comprising dielectric, metal, or semiconducting material, as known in the art.